An efficient floating-point multiplier for digital signal processors

نویسندگان

  • Zonglin Liu
  • Sheng Ma
  • Yang Guo
چکیده

The floating-point multiplication is one of the most basic and frequent digital signal processing operations, and its accuracy and throughput greatly decide the overall accuracy and throughput of the digital signal processors. Based on vectorizing a conventional double precision multiplier, we propose a multiple precision floating-point multiplier. It supports either one double precision multiplication for high accuracy or two parallel single precision multiplications for high throughput. The evaluation results show that the proposed multiplier is suitable for embedded DSPs. It consumes 8.9% less area than two single precision multipliers. Compared the configuration with a single precision multiplier and a double precision multiplier, the proposed multiplier consumes 30.1% less area.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Interval Arithmetic Multiplier for Digital Signal Processors

Interval methods offer quite new research aspects regarding Digital Signal Processing. In scenarios like finite numeric representation, limited precision sensors or the quantization process, signal processing has been practicing interval mathematics as quite a reliable gizmo for expressing the uncertainties. Some types of control systems like estimating or soft computing systems, the uncertaint...

متن کامل

An Efficient Implementation of Floating Point Multiplier using Verilog

To represent very large or small values, large range is required as the integer representation is no longer appropriate. These values can be represented using the IEEE754 standard based floating point representation. Floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, t...

متن کامل

An Efficient Field Programmable Gate Array Implementation of Double Precision Floating Point Multiplier using VHDL

Floating point arithmetic is widely used in many areas, especially scientific computation and signal processing. The main applications of floating points today are in the field of medical imaging, biometrics, motion capture and audio applications. Multipliers play an important role in today‟s digital signal processing and various other applications. A system‟s performance is generally determine...

متن کامل

Implementation of Modified Booth Recoded Wallace Tree Multiplier for fast Arithmetic Circuits

Power consumption has become a critical concern in today’s VLSI system design. The growing market for fast floating-point co-processors, digital signal processing chips, and graphics processor has created a demand for high speed, area-efficient multipliers. The Modified Booth Recoding method is widely used to generate the partial products for implementation of large parallel multipliers, which ...

متن کامل

Low Power Floating Point Computation Sharing Multiplier for Signal Processing Applications

Design of low power, higher performance digital signal processing elements are the major requirements in ultra deep sub-micron technology. This paper presents an IEEE-754 standard compatible single precision Floating-point Computation SHaring Multiplier (FCSHM) scheme suitable for low-power and high-speed signal processing applications. The floating-point multiplier used at the filter taps effe...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • IEICE Electronic Express

دوره 11  شماره 

صفحات  -

تاریخ انتشار 2014